1. Field of the Invention
The present invention generally relates to semiconductor devices and manufacturing and, more particularly, to methods and structures which prevent degradation in semiconductor device wiring.
2. Background Description
Degradation can occur in metal lines in contact with insulator materials containing fluorine. This degradation is a serious concern because it represents a potential failure mechanism for an integrated circuit, IC. The degradation problem is costly to the industry by virtue of the process monitoring, inspections, and equipment maintenance requirements that it entails.
The performance of advanced semiconductor devices is becoming increasingly limited by the delays in the back-end-of-line (BEOL) interconnections. These delays are dependent on both the resistance and capacitance of the wiring structures, which are partially determined by the material properties (resistivity and dielectric constant) of the conductors and insulators used. Copper is being used as the conductor for several emerging technology generations to address at least the issue of resistivity. Copper metallurgy formation is possible using a dual damascene integration scheme. In an ongoing effort to lower overall capacitance wherever possible, several low dielectric constant insulators are being investigated for reducing BEOL capacitance. One leading candidate is fluorosilicate glass (FSG) which can reduce the insulator dielectric constant while maintaining many advantages of inorganic, plasma-enhanced CVD films.
Dual damascene wiring consists of wiring trenches and vertical vias between the trenches, which are filled with copper. Typically the copper in the trenches and vias is cladded with a thin layer of refractory metal or metal nitrides containing Ta, Ti, or W. There are a number of specific challenges in using FSG insulators with dual-damascene copper integration. Chiefly, the compatibility of commonly used metallization schemes (liners, diffusion barriers, seed layers, etc) with free fluorine species is of concern. Additionally, the reliability of damascene interconnects is generally thought to be sensitive to the stresses imposed by the insulators and other layers necessary when forming conducting lines and vias. It is recognized that fluorine stability of FSG materials can be increased by careful control of deposition variables. For some FSG films which are otherwise suitable for integration with copper dual damascene interconnections, this stability is inversely related to the mechanical stresses in the FSG insulator films. This relationship, along with the contamination susceptibility of copper interconnections to fluorine species, poses particular difficulties for this integration.
For example, undoped PECVD silane oxide has a relative dielectric constant of 4.3. As SiF4 doping is added to the plasma, the resulting fluorine incorporation into the film decreases the dielectric constant. The fluorine content in the film is typically quantified by FTIR measurement of the Si—F:SiO bond ratio. Film stress correlates with the fluorine content. Table 1 exemplifies the relationship between fluorine content, dielectric constant and stress of some FSG films. Based on reliability data collected on standard homogeneous FSG films (i.e. single layer) integrated into dual damascene copper wiring, we have determined that films with Si—F:Si—O bond ratios above 1.2% can attack the interface between the via and the underlying copper wire resulting in increased via resistance and via opens. Although decreasing the Si—F:Si—O ratio to less than 0.6% eliminates the via interface problem, the high stress of the low fluorine-content FSG film causes significant manufacturing and reliability problems with the resulting structures.
TABLE 1Dielectric constant and film stress as a function offluorine content (Si—F:Si—O bond ratio) for FSG films.Si—F:SiOkstress04.1−1.0E9 dynes/cm2<0.5%4.1−1.8E90.6%3.8−1.2E91.2%3.8−1.1E91.9%3.7−1.0E92.2%3.6−0.9E92.5%3.6−0.9E9